FIG. 1 is a block diagram of a conventional phase locked loop (PLL) device 101. Referring to FIG. 1, the PLL device 101 includes a phase detector 111, a charge pump 121, a voltage controller oscillator 131, and a divider 141. The phase detector 111 compares a phase of an external clock signal ECLK input from an external source with that of a dividing signal P1 output from the divider 141, detects a phase difference between the external clock signal ECLK and the dividing signal P1, and outputs a phase difference signal P2. The charge pump 121 receives the phase difference signal P2 and outputs a pumping signal P3. The voltage-controlled oscillator 131 receives the pumping signal P3 and outputs an internal clock signal ICLK. The divider 141 transmits to the phase detector 111 the dividing signal P1 obtained by dividing the internal clock signal ICLK at a predetermined rate.
The PLL device 101 performs a locking operation until a frequency of the internal clock signal ICLK is locked to that of the external clock signal ECLK. To this end, the PLL device 101 includes a load capacitor (not shown) at an output terminal of the voltage-controlled oscillator 131. The voltage controlled oscillator 131 controls the amount of electric current that flows through the load capacitor to adjust the frequency of the internal clock signal ICLK.
Specifically, when the frequency of the external clock signal ECLK is higher than that of the internal clock signal ICLK, a large amount of electric current is supplied to the load capacitor such that the frequency of the internal clock signal is raised. When the frequency of the external clock signal ECLK is lower than that of the internal clock signal ICLK, a small amount of electric current is supplied to the load capacitor such that the frequency of the internal clock signal is lowered.
In this way, when the frequency of the external clock signal ECLK is higher than that of the internal clock signal ICLK, a large amount of electric current flows through the output terminal of the voltage controlled oscillator 131, thereby increasing power consumption. When the frequency of the external clock signal ECLK is lower than that of the internal clock signal ICLK, a smaller amount of electric current flows through the output terminal of the voltage-controlled oscillator 131. Thus, the internal clock signal ICLK may be greatly affected by noise, which, in turn, narrows an operating frequency range of the internal clock signal ICLK.